Many battery-powered portable electronic devices, such as laptop computers, cell phones, tablets, and the like, require memory devices that provide large storage capacity and low power consumption. A large storage capacity is typically desired in these devices to maximize the amount of available storage. For this reasons, it is usually desirable to utilize dynamic random access memory (DRAM) because DRAM devices generally have a relatively large storage capacity over other types of memories.
DRAM devices have the disadvantage that their memory cells must be refreshed because of the means by which they store data. As is known in the art, DRAM memory cells each consists of a capacitor that is charged to one of two voltages to store a bit of data. Charge leaks from the capacitor by various means. It is for this reason that DRAM memory cells must be refreshed by recharging them to the original voltage. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array, and then restoring those same data bits back to the same cells in the row. Refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes.
Refreshing DRAM memory cells tends to consume power at a substantial rate. For example, each time a row of memory cells is refreshed, a pair of digit lines for each memory cell is switched to complementary voltages and then equilibrated, which consumes a significant amount power. As the number of columns in the memory cell array increases with increasing memory capacity, the power consumed in actuating each row increases accordingly. Multiple power circuits may also be included in the DRAM devices in order to provide sufficient power to perform refresh operations, thereby multiplying the power consumption during refresh.
Therefore, reducing power consumption related to refreshing memory cells may be desirable.